Memory can generally be characterized as either volatile or non-volatile. Volatile memory, for example, most types of random access memory (RAM), requires constant power to maintain stored information. Non-volatile memory does not require power to maintain stored information. Various types of non-volatile memories include read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs).
Flash memory is a type of EEPROM that is programmed and erased in blocks as opposed to cells. The “NAND” and “NOR” architectures are two common types of flash memory architectures. A NAND flash device typically utilizes a NAND Flash controller to write data to the NAND flash device page by page. Pages are typically grouped into blocks, where a block is the smallest erasable unit. For example, and without limitation, a typical memory device contains 2,112 bytes of memory per page and 128 pages of memory are contained in a block. The smallest entity that can be programmed is a byte.
A typical 2 gigabyte (Gb) NAND flash device is organized into 2,048 blocks. Each block contains 64 pages. Each page has 2,112 bytes total, comprised of a 2,048-byte data area and a 64-byte spare area. The spare area is typically used for error correction code (ECC), redundancy cells, and/or other software overhead functions.
FIG. 1 shows a typical page configuration for a NAND flash memory 10. Memory cells 5 are arranged in rows and columns in a memory array 15. The memory array 15 is partitioned into two arrays, a main array 20 and a spare array, e.g., a column redundancy array 50. Memory cells 5 in the main array 20 are used for storing user data 22 and ECC bytes 24. Memory cells 5 in the column redundancy array 50 are invisible to the user and are used for replacing malfunctioning cells. A decoder 30 decodes addresses from an address bus 65 to generate select signals 40 for the main array 20, and a redundancy decoder 60 decodes addresses to generate redundancy enable signals 70 for the column redundancy array 50.
As NAND technology progresses, memory cell sizes shrink. Likewise, error rates increase, due in part to the smaller cell sizes and the trend towards storing multiple bits of data on a cell as opposed to a single data bit on a cell. To address the increasing error rate problem, stronger ECC algorithms are required to correct more failed bits occurring on a page. A stronger ECC requires more available ECC bytes on a page. Currently, there is no established industry standard regarding the implementation of ECC algorithms for NAND flash memories. ECC implementations vary from application to application, accordingly, the number of bytes required for the various ECC algorithms also varies. In order to accommodate the large range of potential ECC algorithms, memory chip designers are forced to include memory areas for storing the maximum number of ECC bytes per page. However, these extra ECC bytes on a page required for a particular algorithm may not be necessary for another algorithm. The inclusion of memory areas for storing the maximum number of ECC bytes in a chip leads to a waste of valuable chip size for the chips employing algorithms requiring less bytes. On the other hand, a designer making an economical estimate on the required number of ECC bytes may select a number too conservatively, resulting in a chip without enough bytes required for a given algorithm and preventing the implementation of a desired ECC method in the chip all together. Accordingly, there is a desire and a need for a new memory configuration which addresses the aforementioned problems.